1. Technical Field of the Invention
The present invention relates to a leadframe for chips, having low-resistance connections.
2. Description of the Related Art
It is known that the manufacture of integrated-circuit devices provides for a metallic supporting frame (leadframe) on which the semiconductor chip is placed and appropriately connected to the leadframe by means of wires.
The current trend is to increasingly miniaturize chips, which accordingly have high efficiency as regards their electrical resistance.
Chip leadframes, however, have leads whose spacing and dimensions are limited by the mechanical stamping capabilities of the devices meant to manufacture the leadframes.
Consequently, the ever-smaller chips are connected on chip supporting pads having correspondingly reduced dimensions, but the leads of the leadframes are distant from the chip.
Consequently, the electrical resistance of the chip is determined not only by the electrical resistance of the silicon chip itself but also by the electrical resistance of the wires that connect the silicon chip to the leadframe.
Accordingly, the greater the distance between the chip and the leads, the greater the electrical resistance offered by the connecting wires.
Moreover, in the case of an application with leadframes which require wires having two diameters, a larger one for the power section and a smaller one for the signal section, for the wires that must withstand high power levels (i.e., the larger-diameter ones) it is preferable to reduce the resistance as much as possible, but this does not appear to be possible with currently known leadframes.
Moreover, in the case of a high-density leadframe in which the end of the leads is relatively distant from the central area where the chip will be arranged, a simple increase in the length of the leads toward the chip would lead to a situation in which the dimensions of the end of the leads that is directed toward the chip are insufficient to accommodate the larger-diameter wire.
The case of a leadframe provided with a chip having connecting wires with a length of approximately 3 mm and a diameter of 1.2 mils is described by way of example.
A gold wire having a diameter of 1.2 mils has an electrical resistance of approximately 30 mohm/mm and therefore the electrical resistance of the connecting wire, which is 3 mm long, is 90 mohm. This resistance has to be counted twice (for the input and for the output).
Accordingly, the total electrical resistance may be determined to be90 mohm+20 mohm+90 mohm=200 mohm. 
The electrical resistance is too high for some applications, especially owing to the fact that the total resistance of the device is determined not only by the above-cited electrical resistance but also by the resistance of the chip itself.